The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to methods of enabling use of substantially optically opaque wafer level underfill applied in flip chip techniques and apparatus therefor, such as the use of solder bump connections fabricated during back-end-of-line (BEOL) processing of semiconductor chips.
An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Fabrication foundries (“fabs”) manufacture ICs based on design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. The photomasks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, and via pads, as well as other elements that are not functional circuit elements, but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
These photolithographic processes are typically regarded as front-end-of-line (FEOL) processing yielding a chip or die including multiple ICs. The addition of metallization levels and formation of an interconnect structure are said to be produced by back-end-of line (BEOL) processing. In flip-chip type fabrication, solder bumps are formed on a surface of the chips, which are then packaged and mounted on a circuit board that includes attachment pads, such as in the case of 3D integration and/or silicon chip to silicon chip bonding, but which can also include corresponding solder bumps to connect to those of the chips, such as in the case of chip-to-laminate-substrate bonding, in which case the bumps are referred to as “pre-solder bumps.” Solder bumps are thus utilized to provide mechanical and electrical connections between the last or top metallization level and the circuit board.
A common type of solder bump is the controlled collapse chip connection (C4) solder bump. Controlled collapse chip connection (C4) processes are well known in forming solder bumps in semiconductor fabrication. During assembly of the chip and circuit board, C4 solder bumps establish physical attachment and electrical contact between an array of C4 pads on the chip and a complementary array of C4 pads on the circuit board.
Referring to FIGS. 1 and 2, a die of semiconductor devices is shown as might be produced in conventional solder bump fabrication processes, particularly those employing C4 and/or standard plug final via processes. As shown, a die 10 can include a device layer 12, an attachment layer 14, connection pads 16, and solder bumps 18 formed and/or applied by known techniques, such as C4 fabrication processes. In addition, alignment marks 20 can be applied to an attachment surface 15 of die 10, which can also be formed and/or applied using known techniques. It should be understood that attachment layer 14 can typically include a passivation layer, but could instead be some other type of material layer, or that additional layers can be applied over device layer 12 and/or attachment layer 14. For example, attachment layer 14 can include an electrically conductive protective layer using techniques disclosed in U.S. Pat. No. 8,994,173 to Daubenspeck et al., the disclosure of which is incorporated by reference. Still further, die 10 can be formed by any number of known processes and materials used in semiconductor device fabrication, all of which are well known in the art and to those of ordinary skill therein. The specific processes and materials used to form die 10 are not necessarily of import to embodiments of the invention disclosed herein beyond knowledge of material properties of device layer 12, attachment layer 14, pads 16, and solder bumps 18, so that appropriate wafer-level underfill (WLUF) coating material and/or filler can be selected. For example, a typical passivation layer can include polyimide in various incarnations, some photoresponsive and some non-photoresponsive, all of whose properties are well known in the art. In addition, solder bump composition and properties thereof are well known, as are the compositions and properties of a wide variety of other materials that can be used in attachment layer 14.
Top surface 15 of attachment layer 14 is typically left exposed after formation of a solder bump 18, and so is a contact surface during packaging of a semiconductor device in which the passivation layer is included. For example, a typical plug via process can produce a solder bump connected to a metal line by a copper-filled via. The via is formed in attachment layer 14, such as in a final passivation layer, a top surface of the passivation layer, such as surface 15, being exposed after formation of the solder bump. The materials typically used to form a passivation layer, such as a polyimide (PI), tend to be relatively soft, in some cases even gelatinous, and hence more susceptible to damage than dielectric and/or conductor layers. Thus, as shown in FIG. 1, top surface 15 can be damaged during processing and/or fabrication, such as by a pad used in chemical mechanical polishing (CMP) to remove excess copper (Cu) after filling the via and/or to remove material of other layers. For example, a pad used in the CMP process can scratch or abrade the surface of the passivation layer, embed copper or other materials in the passivation layer, introduce discontinuities at the edge of the via, create cavities in the surface, and/or otherwise create defects in areas of the passivation layer where most or all of the copper has been removed.
Such passivation layer damage can reduce reliability of a semiconductor device packaging interface, and so processes have been employed to recondition the surface of the passivation layer, such as wet cleans and plasma treatments, which can be expensive and time consuming. The resulting reconditioned surface of the passivation layer, while far better than a surface without reconditioning, is still not as desirable as the initial, undamaged passivation layer surface prior to CMP. In addition, exposed surfaces can degrade between completion of the solder bumps and passivation layer and the time at which attachment is performed, such as by oxidation and/or other chemical processes, which can adversely affect the electrical and/or mechanical connections produced during the attachment process.
To reduce such damage and other adverse effects, some fabrication processes employ coatings applied over the passivation layer and solder attachment surfaces. For example, a so-called wafer-level underfill (WLUF) layer can be applied to protect exposed surfaces of chips prior to attachment, though other coatings and/or processes are used in fabs, such as reflow/capillary and differential heating/cooling. However, WLUF has significant advantages over some other processes, such as reducing mismatch of coefficient of thermal expansion (CTE) of materials, reducing stress during assembly, and eliminating flux residue cleaning, baking, plasma bombardment, and other steps that can add cost and complexity to fabrication, packaging, and attachment. Even so, some WLUF coating materials present a challenge relative to attachment in that an alignment mark ordinarily visible on the attachment surface, such as on or through the passivation layer, become obscured by the WLUF coating. For example, to provide better CTE matching, a filler can be included in the WLUF material that can render the WLUF coating substantially optically opaque, or at least render discernment of the alignment marks difficult.